
`include "common_header.verilog"

//  *************************************************************************
//  File : gearbox66_ig1_bp
//  *************************************************************************
//  This program is controlled by a written license agreement.
//  Unauthorized reproduction or use is expressly prohibited. 
//  Copyright (c) 2008 MorethanIP
//  Muenchner Strasse 199, 85757 Karlsfeld, Germany
//  info@morethanip.com
//  http://www.morethanip.com
//  *************************************************************************
//  Designed by : Thomas Schrobenhauser (40:66)
//  Extended by : Muhammad Anisur Rahman (32:66)
//  Extended by : Denis Poverennyy (20:66), (66:66) and clk_ena
//  info@morethanip.com
//  *************************************************************************
//  Description: PCS Receive Gearbox to 66
//  Version    : $Id: gearbox66_ig1_bp.v,v 1.4 2012/10/29 12:42:08 dk Exp $
//  *************************************************************************

module gearbox66_ig1_bp (
   reset,
   clk,
   clk_ena,
   gb_bp_ena,
   data_in,
   ff_wr,
   ff_dout,
   ff_afull);

parameter SERDES_WIDTH = 20;

input   reset;                          //  async active high reset
input   clk;                            //  system clock
input   clk_ena;
input   gb_bp_ena;                      //  bypass enable
input   [(SERDES_WIDTH - 1):0] data_in; //  data input
output  ff_wr;                          //  FIFO write enable
output  [65:0] ff_dout;                 //  FIFO data output
input   ff_afull; 


// -----------------------------------
//  System
// -----------------------------------
wire    ff_wr; 
wire    [65:0] ff_dout; 


//  FIFO almost full
// 
reg     data_wr; 
reg     [(SERDES_WIDTH - 1):0] d0; 
reg     [(SERDES_WIDTH - 1):0] d1; 
reg     [(SERDES_WIDTH - 1):0] d2; 
reg     [5:0] cnt; 
reg     [65:0] mux_out; 

//`ifdef EN_SERDES16
generate if( SERDES_WIDTH==16 )
begin:g16

wire    next_wr; 
 
reg     [15:0] d3; 
reg     [15:0] d4; 

always @(data_in)
begin
        d0 = data_in;
end

        
always @(posedge reset or posedge clk)
   begin : process_1
   if (reset == 1'b 1)
      begin
      data_wr <= 1'b 0;
      d1 <= {(SERDES_WIDTH){1'b 0}};
      d2 <= {(SERDES_WIDTH){1'b 0}};
      d3 <= {(SERDES_WIDTH){1'b 0}};
      d4 <= {(SERDES_WIDTH){1'b 0}};
      cnt <= {6{1'b 0}};
      mux_out <= {66{1'b 0}};
      end
   else
      begin

        if (clk_ena == 1'b 1)
        begin
                data_wr <= next_wr | (gb_bp_ena & ~ff_afull);
        end
        else
        begin
                data_wr <= 1'b 0;
        end

      if (clk_ena == 1'b 1)
         begin
         d1 <= d0;
         d2 <= d1;
         d3 <= d2;
         d4 <= d3;

        //  33-cycle counter
         if (cnt == 6'b 100000 | gb_bp_ena == 1'b 1)
            begin
            cnt <= {6{1'b 0}};
            end
         else if (ff_afull == 1'b 0 )
            begin
            cnt <= cnt + 6'b 000001;
            end

        //  output mux
        case (cnt)
            6'b 000000:
               begin
               //mux_out <= {66{1'b 0}};
               mux_out <= {{50{1'b 0}}, d0};      // bypass, copy input
               end
            6'b 000001:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 000010:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 000011:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 000100:
               begin
               mux_out <= {d0[1:0], d1[15:0], d2[15:0], d3[15:0], d4[15:0]};
               end
            6'b 000101:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 000110:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 000111:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 001000:
               begin
               mux_out <= {d0[3:0], d1[15:0], d2[15:0], d3[15:0], d4[15:2]};
               end
            6'b 001001:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 001010:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 001011:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 001100:
               begin
               mux_out <= {d0[5:0], d1[15:0], d2[15:0], d3[15:0], d4[15:4]};
               end
            6'b 001101:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 001110:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 001111:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 010000:
               begin
               mux_out <= {d0[7:0], d1[15:0], d2[15:0], d3[15:0], d4[15:6]};
               end
            6'b 010001:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 010010:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 010011:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 010100:
               begin
               mux_out <= {d0[9:0], d1[15:0], d2[15:0], d3[15:0], d4[15:8]};
               end
            6'b 010101:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 010110:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 010111:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 011000:
               begin
               mux_out <= {d0[11:0], d1[15:0], d2[15:0], d3[15:0], d4[15:10]};
               end
            6'b 011001:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 011010:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 011011:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 011100:
               begin
               mux_out <= {d0[13:0], d1[15:0], d2[15:0], d3[15:0], d4[15:12]};
               end
            6'b 011101:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 011110:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 011111:
               begin
               mux_out <= {66{1'b 0}};
               end
            6'b 100000:
               begin
               mux_out <= {d0[15:0], d1[15:0], d2[15:0], d3[15:0], d4[15:14]};
               end
            default:
               begin
               mux_out <= {66{1'b 0}};
               end
            endcase

         end
      end
   end

assign next_wr = ff_afull == 1'b 0 & (cnt == 6'b 000100 |
                  cnt == 6'b 001000 | cnt == 6'b 001100 |
                  cnt == 6'b 010000 | cnt == 6'b 010100 |
                  cnt == 6'b 011000 | cnt == 6'b 011100 |
                  cnt == 6'b 100000) & clk_ena == 1'b 1 ? 1'b 1 : 1'b 0;

end 
endgenerate
//`endif

//`ifdef EN_SERDES20
generate if( SERDES_WIDTH==20 )
begin:g20

wire    next_wr; 
 
reg     [19:0] d3; 
reg     [19:0] d4; 

always @(data_in)
begin
        d0 = data_in;
end

always @(posedge reset or posedge clk)
   begin : process_1
   if (reset == 1'b 1)
      begin
      data_wr <= 1'b 0;	
      d1 <= {20{1'b 0}};	
      d2 <= {20{1'b 0}};	
      d3 <= {20{1'b 0}};	
      d4 <= {20{1'b 0}};	
      cnt <= {6{1'b 0}};	
      mux_out <= {66{1'b 0}};	
      end
   else
      begin

        if (clk_ena == 1'b 1)
        begin
                data_wr <= next_wr | (gb_bp_ena & ~ff_afull);
        end
        else
        begin
                data_wr <= 1'b 0;
        end

      if (clk_ena == 1'b 1)
        begin
         d1 <= d0;	
         d2 <= d1;	
         d3 <= d2;	
         d4 <= d3;	

        //  33-cycle counter
         if (cnt == 6'b 100000 | gb_bp_ena == 1'b 1)
            begin
            cnt <= {6{1'b 0}};	
            end
         else if (ff_afull == 1'b 0 )
            begin
            cnt <= cnt + 6'b 000001;	
            end

        //  output mux

            case (cnt)
            6'b 000000:
               begin
               //mux_out <= {66{1'b 0}};	//   0
               mux_out <= {{46{1'b 0}}, d0};      // bypass, copy input
               end
            6'b 000001:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 000010:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 000011:
               begin
               mux_out <= {d0[5:0], d1[19:0], d2[19:0], d3[19:0]};	//   6 + 20 + 20 + 20
               end
            6'b 000100:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 000101:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 000110:
               begin
               mux_out <= {d0[11:0], d1[19:0], d2[19:0], d3[19:6]};	//  12 + 20 + 20 + 14
               end
            6'b 000111:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 001000:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 001001:
               begin
               mux_out <= {d0[17:0], d1[19:0], d2[19:0], d3[19:12]};	//  18 + 20 + 20 +  8
               end
            6'b 001010:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 001011:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 001100:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 001101:
               begin
               mux_out <= {d0[3:0], d1[19:0], d2[19:0], d3[19:0], d4[19:18]};	//   4 + 20 + 20 + 20 + 2
               end
            6'b 001110:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 001111:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 010000:
               begin
               mux_out <= {d0[9:0], d1[19:0], d2[19:0], d3[19:4]};	//  10 + 20 + 20 + 16
               end
            6'b 010001:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 010010:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 010011:
               begin
               mux_out <= {d0[15:0], d1[19:0], d2[19:0], d3[19:10]};	//  16 + 20 + 20 + 10
               end
            6'b 010100:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 010101:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 010110:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 010111:
               begin
               mux_out <= {d0[1:0], d1[19:0], d2[19:0], d3[19:0], d4[19:16]};	//   2 + 20 + 20 + 20 + 4
               end
            6'b 011000:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 011001:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 011010:
               begin
               mux_out <= {d0[7:0], d1[19:0], d2[19:0], d3[19:2]};	//   8 + 20 + 20 + 18
               end
            6'b 011011:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 011100:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 011101:
               begin
               mux_out <= {d0[13:0], d1[19:0], d2[19:0], d3[19:8]};	//  14 + 20 + 20 + 12
               end
            6'b 011110:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 011111:
               begin
               mux_out <= {66{1'b 0}};	//   0
               end
            6'b 100000:
               begin
               mux_out <= {d0[19:0], d1[19:0], d2[19:0], d3[19:14]};	//  20 + 20 + 20 +  6
               end
            default:
               begin
               mux_out <= {66{1'b 0}};	
               end
            endcase
         end
      end
   end

assign next_wr = ff_afull == 1'b 0 & (cnt == 6'b 000011 | 
	cnt == 6'b 000110 | cnt == 6'b 001001 | 
	cnt == 6'b 001101 | cnt == 6'b 010000 | 
	cnt == 6'b 010011 | cnt == 6'b 010111 | 
	cnt == 6'b 011010 | cnt == 6'b 011101 | 
	cnt == 6'b 100000) ? 1'b 1 : 1'b 0; 

end
endgenerate
//`endif



//`ifdef EN_SERDES40
generate if( SERDES_WIDTH==40 )
begin:g40

wire    next_wr; 

always @(data_in)
begin
        d0 = data_in;
end

always @(posedge reset or posedge clk)
   begin : process_1
   if (reset == 1'b 1)
      begin
      data_wr <= 1'b 0;	
      d1 <= {40{1'b 0}};	
      d2 <= {40{1'b 0}};	
      cnt <= {6{1'b 0}};	
      mux_out <= {66{1'b 0}};	
      end
   else
      begin
        if (clk_ena == 1'b 1)
        begin
                data_wr <= next_wr | (gb_bp_ena & ~ff_afull);
        end
        else
        begin
                data_wr <= 1'b 0;
        end
        

      if (clk_ena == 1'b 1)
         begin
      d1 <= d0;	
      d2 <= d1;	
//  33-cycle counter
      if (cnt == 6'b 100000 | gb_bp_ena == 1'b 1)
         begin
         cnt <= {6{1'b 0}};	
         end
      else if (ff_afull == 1'b 0 )
         begin
         cnt <= cnt + 6'b 000001;	
         end
//  output mux
      case (cnt)
      6'b 000000:
         begin
         //mux_out <= {66{1'b 0}};	//   0
         mux_out <= {{26{1'b 0}}, d0};  // bypass
         end
      6'b 000001:
         begin
         mux_out <= {d0[25:0], d1[39:0]};	//  26 + 40
         end
      6'b 000010:
         begin
         mux_out <= {66{1'b 0}};	//   0
         end
      6'b 000011:
         begin
         mux_out <= {d0[11:0], d1[39:0], d2[39:26]};	//  12 + 40 + 14
         end
      6'b 000100:
         begin
         mux_out <= {d0[37:0], d1[39:12]};	//  38 + 28
         end
      6'b 000101:
         begin
         mux_out <= {66{1'b 0}};	//   0
         end
      6'b 000110:
         begin
         mux_out <= {d0[23:0], d1[39:0], d2[39:38]};	//  24 + 40 + 2
         end
      6'b 000111:
         begin
         mux_out <= {66{1'b 0}};	//   0
         end
      6'b 001000:
         begin
         mux_out <= {d0[9:0], d1[39:0], d2[39:24]};	//  10 + 40 + 16
         end
      6'b 001001:
         begin
         mux_out <= {d0[35:0], d1[39:10]};	//  36 + 30
         end
      6'b 001010:
         begin
         mux_out <= {66{1'b 0}};	//   0
         end
      6'b 001011:
         begin
         mux_out <= {d0[21:0], d1[39:0], d2[39:36]};	//  22 + 40 + 4
         end
      6'b 001100:
         begin
         mux_out <= {66{1'b 0}};	//   0
         end
      6'b 001101:
         begin
         mux_out <= {d0[7:0], d1[39:0], d2[39:22]};	//   8 + 40 + 18
         end
      6'b 001110:
         begin
         mux_out <= {d0[33:0], d1[39:8]};	//  34 + 32
         end
      6'b 001111:
         begin
         mux_out <= {66{1'b 0}};	//   0
         end
      6'b 010000:
         begin
         mux_out <= {d0[19:0], d1[39:0], d2[39:34]};	//  20 + 40 + 6
         end
      6'b 010001:
         begin
         mux_out <= {66{1'b 0}};	//   0
         end
      6'b 010010:
         begin
         mux_out <= {d0[5:0], d1[39:0], d2[39:20]};	//   6 + 40 + 20
         end
      6'b 010011:
         begin
         mux_out <= {d0[31:0], d1[39:6]};	//  32 + 34
         end
      6'b 010100:
         begin
         mux_out <= {66{1'b 0}};	//   0
         end
      6'b 010101:
         begin
         mux_out <= {d0[17:0], d1[39:0], d2[39:32]};	//  18 + 40 + 8
         end
      6'b 010110:
         begin
         mux_out <= {66{1'b 0}};	//   0
         end
      6'b 010111:
         begin
         mux_out <= {d0[3:0], d1[39:0], d2[39:18]};	//   4 + 40 + 22
         end
      6'b 011000:
         begin
         mux_out <= {d0[29:0], d1[39:4]};	//  30 + 36
         end
      6'b 011001:
         begin
         mux_out <= {66{1'b 0}};	//   0
         end
      6'b 011010:
         begin
         mux_out <= {d0[15:0], d1[39:0], d2[39:30]};	//  16 + 40 + 10
         end
      6'b 011011:
         begin
         mux_out <= {66{1'b 0}};	//   0
         end
      6'b 011100:
         begin
         mux_out <= {d0[1:0], d1[39:0], d2[39:16]};	//   2 + 40 + 24
         end
      6'b 011101:
         begin
         mux_out <= {d0[27:0], d1[39:2]};	//  28 + 38
         end
      6'b 011110:
         begin
         mux_out <= {66{1'b 0}};	//   0
         end
      6'b 011111:
         begin
         mux_out <= {d0[13:0], d1[39:0], d2[39:28]};	//  14 + 40 + 12
         end
      6'b 100000:
         begin
         mux_out <= {d0[39:0], d1[39:14]};	//  40 + 26
         end
      default:
         begin
         mux_out <= {66{1'b 0}};	
         end
      endcase
     end
    end
   end

assign next_wr = ff_afull == 1'b 1 | cnt == 6'b 000000 | 
	cnt == 6'b 000010 | cnt == 6'b 000101 | 
	cnt == 6'b 000111 | cnt == 6'b 001010 | 
	cnt == 6'b 001100 | cnt == 6'b 001111 | 
	cnt == 6'b 010001 | cnt == 6'b 010100 | 
	cnt == 6'b 010110 | cnt == 6'b 011001 | 
	cnt == 6'b 011011 | cnt == 6'b 011110 ? 1'b 0 : 
	1'b 1; 

end
endgenerate
//`endif

//`ifdef EN_SERDES32
generate if( SERDES_WIDTH==32 )
begin:g32

always @(data_in)
begin
        d0 = data_in;
end

always @(posedge reset or posedge clk)
   begin : process_1
   if (reset == 1'b 1)
      begin
      data_wr <= 1'b 0;	
      d1 <= {32{1'b 0}};	
      d2 <= {32{1'b 0}};	
      cnt <= {6{1'b 0}};	
      mux_out <= {66{1'b 0}};	
      end
   else
      begin

        if (clk_ena == 1'b 1)
        begin
                data_wr <= ~ff_afull & (cnt[0] | gb_bp_ena);
        end
        else
        begin
                data_wr <= 1'b 0;
        end

     if (clk_ena == 1'b 1)
         begin
      d1 <= d0;	
      d2 <= d1;	
      if (cnt == 6'b 100000 | gb_bp_ena == 1'b 1)
         begin
         cnt <= {6{1'b 0}};	
         end
      else if (ff_afull == 1'b 0 )
         begin
         cnt <= cnt + 6'b 000001;	
         end
      case (cnt)
      6'b 000000:
         begin
         mux_out <= {{34{1'b 0}}, d0};  // bypass
         end
      6'b 000001:
         begin
         mux_out <= {d0[1:0], d1[31:0], d2[31:0]};	
         end
      6'b 000011:
         begin
         mux_out <= {d0[3:0], d1[31:0], d2[31:2]};	
         end
      6'b 000101:
         begin
         mux_out <= {d0[5:0], d1[31:0], d2[31:4]};	
         end
      6'b 000111:
         begin
         mux_out <= {d0[7:0], d1[31:0], d2[31:6]};	
         end
      6'b 001001:
         begin
         mux_out <= {d0[9:0], d1[31:0], d2[31:8]};	
         end
      6'b 001011:
         begin
         mux_out <= {d0[11:0], d1[31:0], d2[31:10]};	
         end
      6'b 001101:
         begin
         mux_out <= {d0[13:0], d1[31:0], d2[31:12]};	
         end
      6'b 001111:
         begin
         mux_out <= {d0[15:0], d1[31:0], d2[31:14]};	
         end
      6'b 010001:
         begin
         mux_out <= {d0[17:0], d1[31:0], d2[31:16]};	
         end
      6'b 010011:
         begin
         mux_out <= {d0[19:0], d1[31:0], d2[31:18]};	
         end
      6'b 010101:
         begin
         mux_out <= {d0[21:0], d1[31:0], d2[31:20]};	
         end
      6'b 010111:
         begin
         mux_out <= {d0[23:0], d1[31:0], d2[31:22]};	
         end
      6'b 011001:
         begin
         mux_out <= {d0[25:0], d1[31:0], d2[31:24]};	
         end
      6'b 011011:
         begin
         mux_out <= {d0[27:0], d1[31:0], d2[31:26]};	
         end
      6'b 011101:
         begin
         mux_out <= {d0[29:0], d1[31:0], d2[31:28]};	
         end
      6'b 011111:
         begin
         mux_out <= {d0[31:0], d1[31:0], d2[31:30]};	
         end
      default:
         begin
         mux_out <= {66{1'b 0}};	
         end
      endcase
     end
    end
   end

end
endgenerate
//`endif


//`ifdef EN_SERDES64
generate if( SERDES_WIDTH==64 )
begin:g64

wire    next_wr;

always @(data_in)
begin
        d0 = data_in;
end


always @(posedge reset or posedge clk)
   begin : process_1
   if (reset == 1'b 1)
      begin
      data_wr <= 1'b 0;
      d1 <= {64{1'b 0}};
      cnt <= {6{1'b 0}};
      mux_out <= {66{1'b 0}};
      end
   else
      begin
      if (clk_ena == 1'b 1)
        begin
        data_wr <= next_wr | (gb_bp_ena & ~ff_afull);
        end
      else
        begin
        data_wr <= 1'b 0;
        end

      if (clk_ena == 1'b 1)
        begin
        d1 <= d0;

        if (cnt == 6'b 100000 | gb_bp_ena == 1'b 1)
           begin
           cnt <= {6{1'b 0}};
           end
        else if (ff_afull == 1'b 0)
           begin
           cnt <= cnt + 6'b 000001;
           end

        case (cnt)
        6'b 000000:
           begin
           mux_out <= {{2{1'b 0}}, d0};  // bypass
           end
        6'b 000001:
           begin
           mux_out <= {d0[1:0], d1[63:0]};
           end
        6'b 000010:
           begin
           mux_out <= {d0[3:0], d1[63:2]};
           end
        6'b 000011:
           begin
           mux_out <= {d0[5:0], d1[63:4]};
           end
        6'b 000100:
           begin
           mux_out <= {d0[7:0], d1[63:6]};
           end
        6'b 000101:
           begin
           mux_out <= {d0[9:0], d1[63:8]};
           end
        6'b 000110:
           begin
           mux_out <= {d0[11:0], d1[63:10]};
           end
        6'b 000111:
           begin
           mux_out <= {d0[13:0], d1[63:12]};
           end
        6'b 001000:
           begin
           mux_out <= {d0[15:0], d1[63:14]};
           end
        6'b 001001:
           begin
           mux_out <= {d0[17:0], d1[63:16]};
           end
        6'b 001010:
           begin
           mux_out <= {d0[19:0], d1[63:18]};
           end
        6'b 001011:
           begin
           mux_out <= {d0[21:0], d1[63:20]};
           end
        6'b 001100:
           begin
           mux_out <= {d0[23:0], d1[63:22]};
           end
        6'b 001101:
           begin
           mux_out <= {d0[25:0], d1[63:24]};
           end
        6'b 001110:
           begin
           mux_out <= {d0[27:0], d1[63:26]};
           end
        6'b 001111:
           begin
           mux_out <= {d0[29:0], d1[63:28]};
           end
        6'b 010000:
           begin
           mux_out <= {d0[31:0], d1[63:30]};
           end
        6'b 010001:
           begin
           mux_out <= {d0[33:0], d1[63:32]};
           end
        6'b 010010:
           begin
           mux_out <= {d0[35:0], d1[63:34]};
           end
        6'b 010011:
           begin
           mux_out <= {d0[37:0], d1[63:36]};
           end
        6'b 010100:
           begin
           mux_out <= {d0[39:0], d1[63:38]};
           end
        6'b 010101:
           begin
           mux_out <= {d0[41:0], d1[63:40]};
           end
        6'b 010110:
           begin
           mux_out <= {d0[43:0], d1[63:42]};
           end
        6'b 010111:
           begin
           mux_out <= {d0[45:0], d1[63:44]};
           end
        6'b 011000:
           begin
           mux_out <= {d0[47:0], d1[63:46]};
           end
        6'b 011001:
           begin
           mux_out <= {d0[49:0], d1[63:48]};
           end
        6'b 011010:
           begin
           mux_out <= {d0[51:0], d1[63:50]};
           end
        6'b 011011:
           begin
           mux_out <= {d0[53:0], d1[63:52]};
           end
        6'b 011100:
           begin
           mux_out <= {d0[55:0], d1[63:54]};
           end
        6'b 011101:
           begin
           mux_out <= {d0[57:0], d1[63:56]};
           end
        6'b 011110:
           begin
           mux_out <= {d0[59:0], d1[63:58]};
           end
        6'b 011111:
           begin
           mux_out <= {d0[61:0], d1[63:60]};
           end
        6'b 100000:
           begin
           mux_out <= {d0[63:0], d1[63:62]};
           end
        default:
           begin
           mux_out <= {66{1'b 0}};
           end
        endcase
        end
      end
   end

assign next_wr = ff_afull == 1'b 1 | cnt == 6'b 000000 ? 1'b 0 : 1'b 1;

end
endgenerate
//`endif


//`ifdef EN_SERDES66
generate if( SERDES_WIDTH==66 )
begin:g66

        always@( data_in ) 
        begin
                mux_out = data_in;
        end

        always@( clk_ena or ff_afull )
        begin
                data_wr = clk_ena & ~ff_afull;
        end

end
endgenerate
//`endif


assign ff_wr = data_wr; 
assign ff_dout = mux_out; 

endmodule // module gearbox66_ig1

